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Updated: Jun 10, 2026

Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices
Published on: July 11, 2025
Etching and narrowing of graphene from the edges
1Department of Chemistry and Laboratory for Advanced Materials, Stanford University, Stanford, California 94305, USA.
Abstract:
Large-scale graphene electronics requires lithographic patterning of narrow graphene nanoribbons for device integration. However, conventional lithography can only reliably pattern approximately 20-nm-wide GNR arrays limited by lithography resolution, while sub-5-nm GNRs are desirable for high on/off ratio field-effect transistors at room temperature. Here, we devised a gas phase chemical approach to etch graphene from the edges without damaging its basal plane. The reaction involved high temperature oxidation of graphene in a slightly reducing environment in the presence of ammonia to afford controlled etch rate (less than or approximately 1 nm min(-1)). We fabricated approximately 20-30-nm-wide graphene nanoribbon arrays lithographically, and used the gas phase etching chemistry to narrow the ribbons down to <10 nm. For the first time, a high on/off ratio up to approximately 10(4) was achieved at room temperature for field-effect transistors built with sub-5-nm-wide graphene nanoribbon semiconductors derived from lithographic patterning and narrowing. Our controlled etching method opens up a chemical way to control the size of various graphene nano-structures beyond the capability of top-down lithography.

