Bit-serial architecture for optical computing

The design of a complete, stored-program digital optical computer is described. A fully functional, proof-of-principle prototype can be achieved by using LiNbO(3) directional couplers as logic elements and fiber-optic delay lines as memory elements. The key design issues are computation in a realm where propagation delays are much greater than logic delays and implementation of circuits without fip-flops. The techniques developed to address these issues yield architectures that do not change as their clocking speed is scaled upward and the size is scaled downward proportionally; these are called speed-scalable architectures. Signal amplitude restoration and resynchronization are accomplished by the novel technique of switching in a fresh copy of the system clock. Device characteristics that are important to the proof-of-principle demonstration are discussed, including the special properties and limitations that are important when designing with them. Design principles are exemplified by the design of an n-bit counter. Following this, the design for a stored-program bit-serial computer is described. We estimate that the described prototype architecture can be operated in the 100-MHz region with off-the-shelf components, and in the O. 1-1-THz region with foreseeable future components.