High-performance reconfigurable hardware architecture for restricted Boltzmann machines

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Neural networks show great research success but limited industrial adoption due to software-based implementations on general-purpose processors.
• Exploiting inherent parallelism in neural networks requires specialized hardware for improved performance.
• Restricted Boltzmann Machines (RBMs) are a popular neural network type with potential for hardware acceleration.

Purpose of the Study:

• To investigate the mapping of Restricted Boltzmann Machines (RBMs) onto high-performance hardware architectures using Field-Programmable Gate Arrays (FPGAs).
• To develop a modular framework for efficient RBM computation on FPGAs, reducing time complexity through customized hardware engines.
• To present a method for partitioning large RBMs across multiple FPGA resources.

Main Methods:

• Proposed a modular hardware framework with customized engines to accelerate RBM computations.
• Developed a partitioning method to distribute large RBMs across multiple FPGA resources.
• Tested the framework on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs operating at 100 MHz.

Main Results:

• Achieved a maximum computational speed of 3.13 billion connection-updates-per-second for a 256x256 node RBM distributed across four FPGAs.
• Demonstrated a 145-fold speedup compared to an optimized C program running on a 2.8-GHz Intel processor.
• The modular framework effectively reduced computational time complexity for RBMs.

Conclusions:

• Hardware implementation of RBMs on FPGAs offers significant performance advantages over software-based approaches.
• The proposed modular framework and partitioning method enable efficient deployment of large RBMs on FPGA platforms.
• This work paves the way for increased commercial and industrial adoption of neural network applications through hardware acceleration.