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Hybrid plasmon/dielectric waveguide for integrated silicon-on-insulator optical elements.

P D Flammer¹, J M Banks, T E Furtak

¹Department of Physics, Colorado School of Mines, Golden, CO 80401, USA. pflammer@mines.edu

|October 14, 2010

Summary

We developed a hybrid plasmon/dielectric optical waveguide for silicon chips. This technology offers long propagation lengths and VLSI compatibility, paving the way for integrated silicon photonics.

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Area of Science:

Photonics
Materials Science
Electrical Engineering

Background:

Integrating optical functionalities onto silicon chips is crucial for advanced computing and communication.
Existing optical waveguides face challenges with miniaturization, fabrication compatibility, and signal loss.
Electrical interconnects are limited by power consumption and speed at higher bandwidths.

Purpose of the Study:

To present a novel hybrid plasmon/dielectric optical waveguide for silicon-on-insulator (SOI) wafers.
To demonstrate its compatibility with Very Large Scale Integration (VLSI) processing.
To achieve high performance in terms of propagation length and mode confinement.

Main Methods:

Utilizing a hybrid plasmonic and dielectric waveguide design.

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Performing simulations to predict waveguide performance.

Conducting experimental verification on silicon-on-insulator wafers.

Investigating tunability through standard VLSI processing techniques.

Main Results:

The waveguide is single-mode and single-polarization, with VLSI-compatible fabrication.
It exhibits no birefringence and low sensitivity to surface roughness and metallic losses.
Simulations predict millimeter-scale propagation with micron confinement, and >100 micron propagation with sub-micron confinement.
One configuration shows a simulated propagation length of 34 cm.

Conclusions:

The hybrid plasmon/dielectric waveguide is a promising candidate for on-chip optical interconnects.
Its properties are suitable for integration into silicon photonics platforms.
The inherent MOS capacitor structure opens possibilities for active device integration.