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Optoelectronic butterfly interconnection architecture of modified signed-digit arithmetic systems: fully parallel
Applied Optics
|October 14, 2010
Summary
This study introduces a novel encoding scheme for modified signed-digit addition, enabling faster, carry-free computations. The proposed parallel architecture effectively combines algorithms and hardware for efficient arithmetic operations.
Area of Science:
- Computer Science
- Digital Logic Design
- Optoelectronics
Background:
- Modified signed-digit (MSD) arithmetic offers advantages in parallel computation.
- Existing MSD adders/subtracters face challenges in efficient implementation.
- Carry propagation is a bottleneck in traditional addition methods.
Purpose of the Study:
- To propose a space-position-logic-encoding scheme for MSD addition.
- To develop a fully parallel MSD adder and subtracter architecture.
- To leverage binary logic for trinary MSD properties.
Main Methods:
- Developed a space-position-logic-encoding scheme.
- Designed a parallel architecture using optoelectronic switch modules and butterfly interconnections.
- Implemented a combined parallel algorithm and architecture.
Main Results:
- The proposed encoding scheme effectively utilizes binary logic for MSD digits.
- A fully parallel MSD adder and subtracter was successfully built.
- Simulation and experimental results verified the architecture's effectiveness.
Conclusions:
- The novel encoding scheme facilitates carry-free modified signed-digit addition.
- The developed parallel architecture provides an effective solution for high-speed arithmetic.
- This approach demonstrates a practical combination of parallel algorithms and architectures.
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