VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

Area of Science:

• Neurotechnology
• Integrated Circuit Design
• Biomedical Engineering

Background:

• Stimulus artifacts contaminate neural recordings, hindering real-time analysis.
• Closed-loop neuroprostheses require efficient artifact rejection for accurate neural feedback.

Purpose of the Study:

• To present a very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for real-time stimulus artifact rejection (SAR).
• To enable applicability to closed-loop neuroprostheses with reduced power consumption and silicon area.

Main Methods:

• Developed a stimulus artifact rejection (SAR) algorithm utilizing an infinite impulse response (IIR) temporal filtering technique.
• Implemented the algorithm in VLSI for efficient processing.
• Utilized memory initialization with the first stimulus artifact to reduce system response time.
• Simulated the VLSI architecture using pre-recorded neural data from Aplysia californica in AMS 0.35 microm CMOS technology.

Main Results:

• The VLSI architecture successfully eliminates virtually all stimulus artifacts in real time.
• Extracellular neural activity is recovered with microW-level power consumption from 1.5 V.
• Memory initialization significantly decreased system response time compared to no initialization.

Conclusions:

• The proposed VLSI implementation offers an efficient and low-power solution for real-time SAR in neuroprosthetic applications.
• The system's performance is dependent on the reproducibility of stimulus artifact shapes in vivo.
• This technology holds promise for advancing closed-loop neuroprosthetic devices.