Fast Construction of SAH BVHs on the Intel Many Integrated Core (MIC) Architecture

Area of Science:

• Computer Graphics
• High-Performance Computing

Background:

• Bounding Volume Hierarchies (BVHs) are crucial for efficient ray tracing.
• Building high-quality BVHs quickly is a significant challenge in computer graphics.

Purpose of the Study:

• To develop an efficient method for constructing surface area heuristic (SAH) bounding volume hierarchies (BVHs) on the Intel Many Integrated Core (MIC) Architecture.
• To significantly accelerate the BVH construction process for real-time rendering applications.

Main Methods:

• Progressive 10-bit quantization to minimize cache footprint with minimal quality loss.
• Array-of-Structs-of-Arrays (AoSoA) data layout for efficient SIMD processing and streaming.
• High-performance SIMD kernels optimized for binning and partitioning stages.
• A parallelization framework incorporating build-specific optimizations for the MIC architecture.

Main Results:

• Achieved over an order of magnitude speedup compared to high-end GPU builders for comparable BVHs.
• Outperformed spatial median builders in most cases.
• SAH BVH construction speed comparable to existing GPU/CPU builders for regular grids.
• Significantly improved aggregate "build+render" performance over existing CPU and GPU systems.

Conclusions:

• The proposed methods enable highly efficient SAH BVH construction on the Intel MIC architecture.
• This approach offers substantial performance gains for ray tracing and other graphics applications.
• The system demonstrates superior overall performance compared to various existing techniques and hardware.