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Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability.

Daisaku Seto1, Mao Nakajima, Minoru Watanabe

  • 1Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Johoku, Hamamatsu, Shizuoka, 432-8561 Japan.

Applied Optics
|December 22, 2010
PubMed
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We propose a new partial reconfiguration architecture for optically reconfigurable gate arrays. A dynamic optically reconfigurable gate array VLSI chip achieved 2.21 μs partial reconfiguration.

Area of Science:

  • Integrated Circuit Design
  • Optical Computing
  • VLSI

Background:

  • Optically reconfigurable gate arrays (ORGAs) offer potential for high-speed signal processing.
  • Efficient partial reconfiguration is crucial for dynamic ORGA applications.

Purpose of the Study:

  • To propose a novel partial reconfiguration architecture for ORGAs.
  • To demonstrate the feasibility of this architecture through VLSI chip fabrication and testing.

Main Methods:

  • Design and fabrication of an 11,424-gate dynamic ORGA VLSI chip.
  • Utilized a 0.35 μm three-metal complementary metal oxide semiconductor (CMOS) process.
  • Implemented a proposed partial reconfiguration architecture.

Main Results:

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  • Successfully fabricated a 96.04 mm² VLSI chip.
  • Achieved a partial reconfiguration time of 2.21 μs.
  • Demonstrated the functionality of the dynamic ORGA.

Conclusions:

  • The proposed partial reconfiguration architecture is effective for dynamic ORGAs.
  • The fabricated VLSI chip validates the architecture's performance.
  • This work contributes to advancements in reconfigurable optical computing hardware.