Scalable complementary logic gates with chemically doped semiconducting carbon nanotube transistors

Area of Science:

• Materials Science
• Nanotechnology
• Electronics Engineering

Background:

• Fabricating complementary logic gates with carbon nanotube (CNT) networks faces challenges including CNT density control, metallic CNT presence, stable n-doping, and scalable manufacturing.
• Existing methods struggle with device yield and precise dopant placement, hindering the practical application of CNT-based logic circuits.

Purpose of the Study:

• To develop a scalable, cost-effective fabrication process for complementary logic gates using precisely positioned carbon nanotube (CNT) transistors.
• To address limitations in CNT density control, metallic CNT interference, and n-dopant stability and placement.

Main Methods:

• Utilized inkjet printing to precisely position an air-stable n-type dopant (viologen) onto a separated semiconducting CNT network.
• Fabricated complementary logic gates, including CMOS inverters, NAND, and NOR gates, on a HfO2/Si substrate using n/p transistor arrays.
• Conducted all fabrication processes under ambient conditions for potential large-area and flexible applications.

Main Results:

• Achieved nearly 100% yield for CNT transistors with an on/off ratio exceeding 10^3 at an optimized channel length of ~9 μm.
• Demonstrated symmetric performance between n-doped and p-type CNT transistors regarding on/off current and threshold voltage.
• Integrated CMOS inverter, NAND, and NOR logic gates exhibiting high inverter gain (~45) and excellent output voltages.

Conclusions:

• The developed inkjet printing method offers a scalable and cost-effective solution for fabricating high-performance CNT-based complementary logic gates.
• The process overcomes key limitations in CNT device fabrication, paving the way for advanced electronics.
• The ambient condition fabrication is suitable for large-area and flexible thin-film electronic applications.