Memory-efficient architecture for hysteresis thresholding and object feature extraction.

Area of Science:

• Computer Vision
• Image Processing
• Hardware Architecture

Background:

• Hysteresis thresholding enhances object detection but is computationally intensive and memory-demanding.
• Its recursive nature limits application in streaming processors with constrained memory.
• Existing methods often require multiple passes, increasing processing time and resource usage.

Purpose of the Study:

• To propose novel, memory-efficient, and fast architectures for hysteresis thresholding.
• To enable real-time object detection on resource-limited streaming processors.
• To couple thresholding with connected component analysis and feature extraction in a single pass.

Main Methods:

• Developed two architectures: a high-accuracy pixel-based and a faster block-based version.
• Integrated thresholding with connected component analysis and feature extraction into a single image pass.
• Implemented a novel scheme that processes candidate pixels on the fly, reusing labels to minimize memory buffering.

Main Results:

• Achieved significant speedups: up to 24× for pixel-based and 52× for block-based architectures compared to state-of-the-art.
• Reduced memory requirements by approximately 99%.
• Demonstrated effectiveness on both real and synthetic image datasets.

Conclusions:

• The proposed architectures offer a substantial improvement in speed and memory efficiency for hysteresis thresholding.
• These designs are well-suited for real-time object detection in embedded systems and streaming applications.
• The single-pass approach effectively combines multiple image processing tasks, reducing computational overhead.