Low voltage cycling of programmable metallization cell memory devices

Future nanoscale memory technologies must ultimately be able to operate at power supply voltages in the order of 0.6 V or less. We have demonstrated in this work that it is possible to utilize symmetric program-erase (P-E) cycling for Ag/Ag-Ge-S/W programmable metallization cell devices at voltages below 0.6 V and still maintain an OFF/ON resistance ratio well in excess or 10 over a wide range of program and erase currents (0.27, 1.6, 55 and 220 µA) as set by a series resistance. The distributions of resistance values for 10(4) P-E cycles indicate that the margins between the highest on- and lowest off-state resistances are sufficient for unambiguous differentiation in all but the lowest current case in which there is some overlap. In addition, there is no substantial change in switching speed for up to 1.5 × 10(6) P-E operations, the maximum number of cycles attempted in this study.