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Cell-based hardware architecture for full-parallel generation algorithm of digital holograms.

Young-Ho Seo¹, Hyun-Jun Choi, Ji-Sang Yoo

¹College of Liberal Arts, Kwangwoon University, Seoul, South Korea. yhseo@kw.ac.kr

|June 7, 2011

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This study introduces a novel hardware architecture for faster digital hologram calculations using parallel processing. The new design optimizes computer-generated holograms (CGH) for improved computational efficiency.

Area of Science:

Optics and Photonics
Computer Engineering
Digital Signal Processing

Background:

Digital hologram calculation is computationally intensive.
Existing methods for computer-generated holograms (CGH) face performance limitations.
Parallel computation offers a potential solution for accelerating CGH.

Purpose of the Study:

To propose a new hardware architecture for accelerating digital hologram calculations.
To develop a cell-based very large scale integrated circuit (VLSI) architecture for parallel CGH computation.
To optimize the CGH equation for efficient hardware implementation.

Main Methods:

Modification of the basic computer-generated hologram (CGH) equation to enable parallel pixel value calculation.
Development of a cell-based VLSI architecture featuring initial parameter and update-phase calculators.

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Hardware implementation of the proposed architecture, including optimization through cosine function approximation.

Extension of the architecture for parallelizing calculations in the horizontal direction.

Main Results:

A novel hardware architecture significantly speeds up digital hologram calculations through parallel computation.
The modified CGH equation and cell-based architecture simplify hardware design and optimize performance.
Analysis of hardware resource usage and performance characteristics allows for hardware selection based on desired precision.
The proposed approach demonstrates efficient parallelization capabilities for CGH generation.

Conclusions:

The developed hardware architecture effectively accelerates digital hologram calculations.
The cell-based VLSI design offers a scalable and efficient solution for CGH generation.
Hardware resource and performance analyses provide crucial insights for practical implementation and optimization.