VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality.

Area of Science:

• Neuromorphic Engineering
• Computer Architecture
• Artificial Intelligence Hardware

Background:

• Large-scale neuromorphic systems necessitate advanced spike event communication for neural network operations.
• Current systems often rely on separate, low-bandwidth channels for configuration, limiting overall efficiency.

Purpose of the Study:

• To present a high-speed communication infrastructure for wafer-scale neuromorphic systems.
• To implement configurable axonal delays for dynamic processing and emulating learning.
• To integrate configuration data transmission into the main communication channel.

Main Methods:

• Development of application-specific neuromorphic communication integrated circuits (ICs).
• Implementation within a field-programmable gate array (FPGA)-maintained environment.
• Utilizing a packet-based pulse channel for both spike transmission and configuration data.

Main Results:

• The ICs successfully implemented configurable axonal delays, demonstrating their efficacy in neuromorphic benchmark behavior.
• Configuration data is transmitted at full bandwidth via the packet-based pulse channel, eliminating separate low-bandwidth channels.
• The pulse communication subgroup achieved a 25-50x higher event transmission rate compared to existing infrastructures.

Conclusions:

• The presented infrastructure significantly boosts communication efficiency in wafer-scale neuromorphic systems.
• Integrated, high-bandwidth configuration enhances the system's flexibility and performance.
• This approach represents a substantial advancement in neuromorphic communication technology.