Parallel programmable asynchronous neighborhood mechanism for Kohonen SOM implemented in CMOS technology

Area of Science:

• Hardware implementation of artificial neural networks
• Neuromorphic engineering
• VLSI design

Background:

• Kohonen self-organizing maps (SOMs) are widely used for unsupervised learning.
• Traditional software implementations of SOMs face limitations in speed and parallel processing.
• There is a need for efficient hardware solutions for SOMs to accelerate learning and reduce power consumption.

Purpose of the Study:

• To present a novel programmable neighborhood mechanism for hardware-implemented Kohonen self-organizing maps (SOMs).
• To demonstrate the feasibility of realizing three different map topologies on a single chip.
• To analyze the performance, robustness, and energy efficiency of the proposed hardware architecture.

Main Methods:

• Design and implementation of a fully parallel and asynchronous hardware architecture for SOMs.
• Integration of a programmable neighborhood mechanism allowing for flexible topology selection.
• Fabrication using 0.18 μm complementary metal-oxide semiconductor (CMOS) technology.
• Evaluation of adaptation speed, robustness to variations, and energy consumption.

Main Results:

• The proposed mechanism achieves parallel weight adaptation in under 11 ns for a medium-sized map.
• The hardware SOM demonstrates robustness against process, voltage, and temperature variations.
• Low energy consumption of a few picojoules (pJ) per neuron per learning pattern was achieved.
• Optimization of map topology and neighborhood range reduced chip area by up to 60% and power dissipation by 80% without compromising learning quality.

Conclusions:

• The developed hardware-based SOM with a programmable neighborhood mechanism offers significant speed and efficiency advantages over software implementations.
• The architecture is suitable for integration into VLSI systems, enabling high-performance, low-power neural network applications.
• Optimization of design parameters is crucial for maximizing hardware efficiency and minimizing resource utilization.