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Soft Lithographic Functionalization and Patterning Oxide-free Silicon and Germanium
Published on: December 16, 2011
Thin films of two functional oxides patterned laterally by soft lithography.
Ole F Göbel1, Tomasz M Stawski, Johan E ten Elshof
1MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands.
ACS Applied Materials & Interfaces
|December 14, 2011
Summary
This study demonstrates a two-step soft-lithographic micromolding process to create dual-phase oxide thin films. The fabricated CoFe(2)O(4)/ZnO and CoFe(2)O(4)/BaTiO(3) patterns showed good replication and lateral separation.
Area of Science:
- Materials Science
- Nanotechnology
- Thin Film Deposition
Background:
- Fabricating patterned functional oxide thin films is crucial for advanced electronic and magnetic devices.
- Controlling the lateral arrangement of distinct oxide phases at the microscale presents significant challenges.
Purpose of the Study:
- To develop a reliable method for creating laterally patterned dual-phase oxide thin films.
- To investigate the structural and morphological characteristics of these patterned films.
Main Methods:
- Utilized a two-step soft-lithographic micromolding process.
- Fabricated CoFe(2)O(4)/ZnO and CoFe(2)O(4)/BaTiO(3) dual-phase patterns.
- Characterized film structure using X-ray diffraction and morphology with magnetic force microscopy.
Main Results:
- Achieved good replication of the initial pattern with uniform film thickness.
- Confirmed the presence of two distinct phases and their lateral separation.
- Observed slight height variations at phase edges, indicating areas for process optimization.
- Demonstrated sufficient film smoothness for potential multilayer structure fabrication.
Conclusions:
- The soft-lithographic micromolding technique is effective for producing laterally patterned dual-phase oxide thin films.
- The process allows for controlled arrangement of different functional oxides.
- The resulting films are suitable for further development in multilayer device architectures.

