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Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices
Published on: December 7, 2017
Electron trapping in InP nanowire FETs with stacking faults
Jesper Wallentin1, Martin Ek, L Reine Wallenberg
1Solid State Physics, Lund University, Box 118, S-221 00, Lund, Sweden. jesper.wallentin@ftf.lth.se
Abstract:
Semiconductor III-V nanowires are promising components of future electronic and optoelectronic devices, but they typically show a mixed wurtzite-zinc blende crystal structure. Here we show, theoretically and experimentally, that the crystal structure dominates the conductivity in such InP nanowires. Undoped devices show very low conductivities and mobilities. The zincblende segments are quantum wells orthogonal to the current path and our calculations indicate that an electron concentration of up to 4.6 × 10(18) cm(-3) can be trapped in these. The calculations also show that the room temperature conductivity is controlled by the longest zincblende segment, and that stochastic variations in this length lead to an order of magnitude variation in conductivity. The mobility shows an unexpected decrease for low doping levels, as well as an unusual temperature dependence that bear resemblance with polycrystalline semiconductors.
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