Burst Mode Receiver for 112 Gb/s DP-QPSK with parallel DSP

Area of Science:

• Optical Communications Engineering
• Digital Signal Processing
• Integrated Circuit Design

Background:

• Advancements in digital coherent optical receivers are critical for high-speed wavelength-division multiplexing (WDM) systems.
• Burst mode operation presents unique challenges for receiver acquisition and tracking performance.
• Integration in CMOS ASIC technology is desired for cost-effective, high-performance optical transceivers.

Purpose of the Study:

• To present a 112 Gb/s dual-polarization quadrature phase-shift keying (DP-QPSK) digital coherent optical receiver designed for burst mode operation.
• To demonstrate the feasibility of implementing this receiver in a CMOS ASIC with a 218.75 MHz clock speed.
• To introduce and validate a novel equalizer initialization scheme for rapid convergence in burst mode.

Main Methods:

• Development of a parallel digital signal processing (DSP) architecture suitable for CMOS ASIC implementation.
• Experimental validation in a five-channel, 50 GHz grid WDM burst switching setup.
• Utilized a commercially available wavelength tunable laser as the local oscillator.
• Introduced a new equalizer initialization scheme to address degenerate convergence issues.

Main Results:

• Successfully demonstrated a burst mode 112 Gb/s DP-QPSK digital coherent optical receiver.
• Achieved a burst acquisition time of less than 200 ns.
• Validated that the tunable local oscillator performance is compatible with burst mode reception using differential decoding.
• Confirmed that parallel DSP implementation does not significantly degrade polarization and frequency tracking.

Conclusions:

• The presented receiver architecture and novel equalization scheme enable efficient burst mode operation in WDM systems.
• CMOS ASIC implementation is viable, paving the way for cost-effective, high-speed optical transceivers.
• The system demonstrates robust performance suitable for dynamic optical network applications.