Parametric dense stereovision implementation on a system-on chip (SoC).

Area of Science:

• Computer Vision
• Hardware Architecture
• Robotics

Background:

• Traditional 3D stereo systems face limitations due to restricted stereo correspondences.
• This restricts the capabilities of artificial vision algorithms in depth perception.

Purpose of the Study:

• To propose a novel hardware implementation for dense stereovision 3D measurements.
• To develop a system-on-chip (SoC) that overcomes traditional limitations in processing stereo image flow.

Main Methods:

• A scalable, reconfigurable hardware architecture using double buffering and pipelined processing.
• An on-chip design that processes image flow directly, avoiding external memory storage.
• Configurable parameters managed by an embedded processor for flexible integration.

Main Results:

• Achieved high processing speeds (up to 50 fps for 2 Mpix images) with dense stereo maps.
• Provided direct 3D data output without storing entire stereo images, minimizing latency.
• Demonstrated efficient resource utilization for accurate 3D data recovery.

Conclusions:

• The proposed SoC offers a high-performance, efficient solution for real-time dense 3D reconstruction.
• Implementation on reconfigurable hardware (FPGA) enables use in autonomous systems as a coprocessor.
• This approach facilitates high-density 3D image reconstruction for advanced computer vision applications.