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Related Concept Videos

P-N junction01:11

P-N junction

A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...

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Related Experiment Video

Updated: May 19, 2026

Optimized Fabrication Procedure for High-Quality Graphene-based Moir&#233; Superlattice Devices
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Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices

Published on: July 11, 2025

Creating graphene p-n junctions using self-assembled monolayers.

Hossein Sojoudi1, Jose Baltazar, Laren M Tolbert

  • 1Woodruff School of Mechanical Engineering and School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA.

ACS Applied Materials & Interfaces
|August 23, 2012
PubMed
Summary
This summary is machine-generated.

Chemists created n-type and p-type graphene using silane modifiers, forming a stable graphene p-n junction. This novel method enables thermally stable graphene devices up to 200 °C.

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Area of Science:

  • Materials Science
  • Nanotechnology
  • Solid State Physics

Background:

  • Graphene's unique electronic properties are highly sensitive to doping.
  • Creating stable and controllable graphene p-n junctions is crucial for advanced electronic devices.
  • Existing doping methods can introduce defects and limit thermal stability.

Purpose of the Study:

  • To develop a method for creating n-type and p-type graphene.
  • To fabricate a graphene p-n junction using surface modification.
  • To investigate the thermal stability of the fabricated graphene p-n junction.

Main Methods:

  • Utilized 3-aminopropyltriethoxysilane (APTES) for n-type graphene.
  • Employed perfluorooctyltriethoxysilane (PFES) for p-type graphene.
  • Fabricated a graphene p-n junction by patterning modifiers on a dielectric substrate.
  • Verified the junction using field-effect transistor (FET) characterization.

Main Results:

  • Successfully created distinct n-type and p-type graphene regions.
  • Demonstrated a graphene p-n junction with two separate Dirac points in I-V curves.
  • Confirmed energy separation of neutrality points in complementary regions.
  • Achieved thermal stability of the graphene p-n junction up to 200 °C.

Conclusions:

  • Surface modification with APTES and PFES effectively creates n-type and p-type graphene.
  • The developed method yields thermally stable graphene p-n junctions with minimal doping-induced defects.
  • This approach offers a promising route for advanced graphene-based electronic devices.