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Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Arthur Spivak1, Adam Teman, Alexander Belenky

  • 1The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

Sensors (Basel, Switzerland)
|November 1, 2012
PubMed
Summary

This study presents a low-power global shutter CMOS image sensor with Wide Dynamic Range (WDR) capabilities. It achieves high performance using novel power-saving techniques, reducing design time and cost.

Keywords:
CMOSSNRimage sensorlow powersnapshotstrong inversionsub-thresholdwide dynamic range

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Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Sensor Technology

Background:

  • Smart CMOS sensors are vital in numerous applications, including surveillance and mobile devices.
  • Reducing power consumption in these sensors is a significant design challenge.

Purpose of the Study:

  • To present a low-power global shutter CMOS image sensor with Wide Dynamic Range (WDR) capability.
  • To detail power reduction techniques and their impact on sensor performance and design efficiency.

Main Methods:

  • Implemented several power reduction techniques: dual voltage supply, selective power down, varied threshold voltage transistors, non-rationed logic, and low-voltage static memory.
  • Developed a mathematical model relating sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) to power supplies.
  • Fabricated the sensor using a 0.18 µm CMOS process.

Main Results:

  • Achieved a remarkable dynamic range (DR) and very low power consumption.
  • The sensor demonstrated a Signal to Noise Ratio (SNR) of 48 dB and a Dynamic Range (DR) of 96 dB.
  • Power dissipation was as low as 4.5 nW per pixel.

Conclusions:

  • The proposed power-saving solutions enable a low-voltage smart image sensor with high DR and low power consumption.
  • The standard sensor architecture was maintained, reducing design time and cost.
  • The developed mathematical model aids in balancing sensor performance and power efficiency.