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Quantitative three-dimensional carrier mapping in nanowire-based transistors using scanning spreading resistance
A Schulze1, T Hantschel, P Eyben
1IMEC, Kapeldreef 75, 3001 Leuven, Belgium. Andreas.Schulze@imec.be
Ultramicroscopy
|January 1, 2013
Summary
This study introduces a 3D-carrier mapping technique by extending high-vacuum scanning spreading resistance microscopy (HV-SSRM). This method enables quantitative 3D analysis of nanoelectronic devices, crucial for next-generation semiconductor development.
Area of Science:
- Materials Science
- Nanotechnology
- Semiconductor Physics
Background:
- Nanoelectronic device performance relies heavily on charge carrier distribution.
- High-vacuum scanning spreading resistance microscopy (HV-SSRM) is a key 2D technique for carrier mapping.
- 3D carrier distribution is vital for understanding dopant mechanisms in nanoscale devices.
Purpose of the Study:
- To develop a quantitative 3D-carrier characterization technique.
- To extend the 2D capabilities of SSRM for 3D analysis.
- To support process development for next-generation nanoelectronic devices.
Main Methods:
- Acquired 2D carrier concentration maps on successive cross-sections of a nanowire (NW)-based heterojunction tunneling transistor.
- Arranged multiple devices in a staggered array for incremental cross-sections via a single cleave.
- Developed a specialized interpolation algorithm for reconstructing 3D carrier maps from 2D data, suitable for rotationally symmetric structures like NWs.
Main Results:
- Successfully extended SSRM from 2D to quantitative 3D-carrier profiling.
- Demonstrated the method on a SiGe-Si NW heterojunction tunneling transistor.
- Validated the 3D mapping by confirming the expected absence of carrier variation in the third dimension for NWs.
Conclusions:
- The presented approach enables high-resolution 3D-carrier mapping in nanoelectronic devices.
- This technique is essential for studying dopant distribution in confined 3D volumes.
- The developed methodology supports the advancement of semiconductor process development.

