Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture

Area of Science:

• Biomedical Engineering
• Signal Processing
• Neuromorphic Engineering

Background:

• Adaptive neural stimulation requires real-time processing of neural signals.
• Existing systems often face power consumption and computational limitations.
• Accurate magnitude and phase-synchronization are key for effective neural signal analysis.

Purpose of the Study:

• To develop a low-power VLSI processor architecture for real-time computation of neural signal magnitude and phase-synchronization.
• To integrate this processor into a closed-loop implantable microsystem for adaptive neural stimulation.
• To validate the processor's efficacy in detecting epileptic seizures using human intracranial EEG data.

Main Methods:

• Designed a VLSI processor architecture utilizing three CORDIC (Coordinate Rotation Digital Computer) processing cores.
• Implemented the architecture using shift-and-add operations, avoiding multiplication for efficiency.
• Synthesized and prototyped a 10-bit processor in 1.2 V 0.13 μm CMOS technology.

Main Results:

• The processor utilizes 41,000 logic gates and dissipates 3.6 μW per input pair.
• Achieved a per-channel throughput of 1.7 kS/s at a 2.5 MHz clock speed.
• Demonstrated linear power scaling with the number of input channels and sampling rate.
• Validated efficacy in early epileptic seizure detection on human intracranial EEG data.

Conclusions:

• The developed low-power VLSI processor architecture is suitable for real-time neural signal analysis in implantable microsystems.
• The CORDIC-based design offers significant power efficiency for adaptive neural stimulation applications.
• The processor's performance in seizure detection highlights its potential clinical utility.