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Related Concept Videos

MOS Capacitor01:25

MOS Capacitor

A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
Integration of Synaptic Events01:28

Integration of Synaptic Events

Synaptic integration mainly includes the summation of graded potentials. Graded potentials, regardless of their type, cause subtle alterations in membrane voltage, resulting in either depolarization or hyperpolarization. These incremental changes, when combined or summed, can propel the neuron toward its threshold. Consider, for example, a membrane experiencing a +15 mV shift, causing it to depolarize from -70 mV to -55 mV. In this scenario, graded potentials govern the membrane's ability to...
Neural Circuits01:25

Neural Circuits

Neural circuits and neuronal pools are two of the main structures found in the nervous system. Neural circuits are networks of neurons that work together to carry out a specific task or process. They consist of interconnected neurons and glial cells, which provide structural and metabolic support.
Neuronal pools are collections of nerve cells with similar functions and interact through chemical and electrical signals. These pools include both interneurons (the central neural circuit nodes that...

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Related Experiment Video

Updated: May 8, 2026

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

Jose M Cruz-Albrecht1, Timothy Derosier, Narayan Srinivasa

  • 1HRL Laboratories LLC, Malibu, CA 90265, USA.

Nanotechnology
|September 4, 2013
PubMed
Summary

This study presents a scalable neural chip integrating nanoscale memristors with CMOS technology for advanced synaptic functions. The chip demonstrates biologically realistic neuronal and synaptic computations using reconfigurable connections and plasticity.

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Last Updated: May 8, 2026

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
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Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

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A Method for Growing Bio-memristors from Slime Mold
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Published on: November 2, 2017

Area of Science:

  • Neuroscience
  • Electrical Engineering
  • Materials Science

Background:

  • The development of efficient neuromorphic computing hardware is crucial for advancing artificial intelligence.
  • Integrating synaptic plasticity mechanisms into silicon-based systems presents significant engineering challenges.

Purpose of the Study:

  • To design and simulate a scalable neural chip featuring nanoscale memristors for synaptic electronics.
  • To implement integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP) on-chip.
  • To demonstrate biologically realistic functional behavior through circuit-level simulations.

Main Methods:

  • Utilized nanoscale memristors for eight-level synaptic conductance storage.
  • Integrated memristors with complementary metal-oxide-semiconductor (CMOS) technology using a 90 nm process.
  • Designed a reconfigurable neural network topology with on-chip post-processed memristor arrays.
  • Performed circuit-level simulations of neuronal and synaptic computations.

Main Results:

  • Successfully designed a neural chip comprising approximately 16 million CMOS transistors and 73,728 integrated memristors.
  • Demonstrated the storage of synaptic conductance values in memristors with eight distinct levels.
  • Validated the reconfigurable connectivity between neurons.
  • Achieved biologically realistic functional behavior in circuit-level simulations.

Conclusions:

  • The presented neural chip design offers a scalable platform for neuromorphic computing.
  • The integration of memristors with CMOS technology enables efficient implementation of synaptic plasticity.
  • The chip's architecture supports complex neuronal and synaptic computations, paving the way for advanced AI hardware.