Reward-based learning under hardware constraints-using a RISC processor embedded in a neuromorphic substrate.

Area of Science:

• Neuromorphic Engineering
• Computational Neuroscience
• Artificial Intelligence Hardware

Background:

• Implementing synaptic plasticity, crucial for neural learning, in hardware presents challenges.
• Wafer-scale neuromorphic systems require flexible and efficient plasticity mechanisms.
• Globally modulated spike-timing-dependent plasticity (STDP) is a key learning rule.

Purpose of the Study:

• To propose and analyze a flexible synaptic plasticity implementation for accelerated neuromorphic hardware.
• To evaluate the system's performance using reward-modulated STDP in a spike train learning task.
• To assess the impact of hardware constraints on learning performance.

Main Methods:

• Simulations of a wafer-scale neuromorphic system with an embedded general-purpose processor for plasticity.
• Implementation of a reward-modulated STDP rule for a spike train learning task.
• Evaluation under simulated constraints: discretized weights, restricted interfaces, analog circuit mismatch, and communication latency.

Main Results:

• Probabilistic updates enhance performance with low-resolution synaptic weights.
• A simple interface between analog synapses and the processor is sufficient for learning.
• System performance is robust to analog circuit mismatch.
• Communication latency significantly impacts learning in highly accelerated systems, requiring minimization.

Conclusions:

• The proposed flexible implementation is suitable for emulating reward-modulated STDP.
• This approach is a strong candidate for future wafer-scale neuromorphic systems like BrainScaleS.
• Hardware-based synaptic plasticity can be achieved efficiently with careful consideration of constraints.