A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation.

Area of Science:

• Neuroscience
• Biomedical Engineering
• Integrated Circuit Design

Background:

• Spike detection is crucial for decoding neural activity in extracellular recordings.
• Application-Specific Integrated Circuit (ASIC) implementation offers data-rate reduction and wireless capabilities for neural data acquisition.

Purpose of the Study:

• To present a 16-channel neural spike detection ASIC designed for efficient and low-power neural signal processing.
• To demonstrate the chip's capability for simultaneous output of field potentials, filtered neural data, and spiking probability maps.

Main Methods:

• Design and fabrication of a 16-channel neural spike detection ASIC using a 0.13 µm CMOS process.
• Simultaneous data output streams: down-sampled field potentials (1.25 KHz), band-pass filtered neural data, and spiking probability maps (40 KHz).
• Verification of functionality and performance through in-vivo and benchtop experiments.

Main Results:

• The ASIC achieves a peak power dissipation of 85 µW per channel.
• Demonstrated a substantial data-rate reduction of 98.44%.
• Successful validation of the chip's performance in real-world experimental conditions.

Conclusions:

• The developed 16-channel neural spike detection ASIC effectively reduces data rates for neural recordings.
• The chip facilitates efficient information decoding and supports wireless neural recording applications with low power consumption.