Resource efficient hardware architecture for fast computation of running max/min filters

Area of Science:

• Digital Signal Processing
• Image Processing
• Computer Architecture

Background:

• Running max/min filters are crucial for image processing but computationally intensive, especially with large kernels.
• Direct implementations of these filters scale poorly with kernel size (k x k), requiring O(k^2) comparisons per sample.
• Existing faster methods involve kernel decomposition and 1D algorithms on custom hardware.

Purpose of the Study:

• To present a hardware architecture for real-time computation of running max/min filters.
• To leverage the van Herk/Gil-Werman (HGW) algorithm for efficient filter computation.
• To optimize resource utilization (computation and memory) for Field Programmable Gate Array (FPGA) implementation.

Main Methods:

• Design and implementation of a hardware architecture based on the van Herk/Gil-Werman (HGW) algorithm.
• Targeting the architecture for Field Programmable Gate Array (FPGA) devices.
• Performance evaluation using image processing tasks with varying kernel sizes.

Main Results:

• The proposed architecture achieves real-time performance, processing 1024x1024 images with 255x255 kernels in approximately 8.4 milliseconds (120 FPS) at 250 MHz.
• Demonstrates reduced computation and memory resource requirements compared to prior FPGA architectures.
• Exhibits high scalability with kernel size, offering a favorable performance/area tradeoff.

Conclusions:

• The HGW-based FPGA architecture provides an efficient solution for real-time running max/min filtering.
• The design is suitable for embedded applications requiring high-speed image processing and adaptive thresholding.
• Offers significant performance gains and resource efficiency for demanding image processing tasks.