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Two-photon laser-assisted device alteration in silicon integrated-circuits.

Keith A Serrels, Kent Erington, Dan Bodoh

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    |February 12, 2014
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    A new technique called two-photon laser-assisted device alteration (2pLADA) precisely locates electrical faults in integrated circuits. This advanced optical probing method achieves high spatial and temporal resolution, enabling fault isolation in advanced semiconductor devices.

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    Area of Science:

    • Semiconductor Device Physics
    • Integrated Circuit Analysis
    • Optoelectronics

    Background:

    • Optoelectronic imaging has been crucial for integrated circuit (IC) design, debugging, and failure analysis.
    • Current probing techniques, such as laser-assisted device alteration (LADA), struggle to keep pace with aggressive semiconductor scaling.
    • Existing methods lack the resolution to pinpoint faults to individual transistors in advanced nodes, implicating many potential culprits.

    Purpose of the Study:

    • To introduce a novel high-resolution probing technique for integrated circuits.
    • To overcome the limitations of current methods in localizing electrical faults in scaled devices.
    • To enable precise fault isolation at the transistor level for advanced technology nodes.

    Main Methods:

    • Development and application of two-photon laser-assisted device alteration (2pLADA).
    • Exploitation of two-photon absorption (TPA) for precise carrier injection and localization.
    • High-resolution optical probing to achieve sub-100 nm spatial resolution.

    Main Results:

    • Demonstrated precise three-dimensional localization of photo-carriers injected via TPA.
    • Successfully implicated individual transistors separated by as little as 100 nm.
    • Achieved unprecedented timing resolution (<10 ps) for observing transistor switching dynamics.

    Conclusions:

    • 2pLADA offers exceptional spatial and temporal resolution for optical fault localization.
    • The technique extends optical fault isolation capabilities to sub-14 nm technology nodes.
    • This advancement is critical for debugging and failure analysis in next-generation integrated circuits.