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A scalable silicon photonic chip-scale optical switch for high performance computing systems
Optics Express
|February 12, 2014
Summary
This study introduces a silicon photonic chip-scale optical switch for high-performance computing networks. The novel Arrayed Waveguide Grating Router (AWGR) switch offers lower latency and higher throughput than electronic switches, even at high loads.
Area of Science:
- Photonics and Optical Engineering
- High-Performance Computing Interconnects
Background:
- Scalable interconnect networks are crucial for high-performance computing (HPC).
- Existing electronic switches face limitations in latency and throughput for demanding HPC workloads.
Purpose of the Study:
- To present the architecture and performance of a silicon photonic chip-scale optical switch.
- To demonstrate the effectiveness of wavelength parallelism for contention resolution in HPC networks.
Main Methods:
- Utilized an Arrayed Waveguide Grating Router (AWGR) for wavelength routing and contention resolution.
- Employed a cycle-accurate network simulator for performance evaluation.
- Integrated key components (ring modulators, photodetectors, AWGR) on a CMOS-compatible silicon photonic platform.
Main Results:
- The silicon photonic switch demonstrated lower end-to-end latency and higher throughput compared to electronic switches at high input loads (>90%).
- Proof-of-concept routing functions were successfully demonstrated on an 8x8 prototype.
Conclusions:
- The proposed silicon photonic switch architecture is a viable solution for scalable interconnect networks in HPC.
- Integration on a CMOS-compatible platform ensures a compact, energy-efficient, and cost-effective device.
