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Analysis of Contact Interfaces for Single GaN Nanowire Devices
Published on: November 15, 2013
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Self-assembled nanowire array capacitors: capacitance and interface state profile.
Qiliang Li1, Hao D Xiong, Xuelei Liang
1Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030, USA.
Nanotechnology
|March 4, 2014
Summary
Researchers developed a new method using silicon nanowire arrays to accurately measure capacitance and interface states in nanoscale transistors. This technique overcomes the limitations of single nanowire measurements, enabling better understanding of electronic properties.
Area of Science:
- Nanotechnology
- Materials Science
- Semiconductor Physics
Background:
- Accurate characterization of capacitance and interface states is crucial for understanding nanowire transistor electronic properties.
- Measuring the small capacitance of a single nanowire precisely is a significant challenge.
Purpose of the Study:
- To develop an effective platform for direct characterization of capacitance and interface states in nanoscale metal-oxide-semiconductor structures.
- To overcome the measurement limitations of individual nanowires.
Main Methods:
- Fabrication of metal-oxide-semiconductor capacitors using a large array of self-assembled silicon nanowires.
- Direct measurement of capacitance and conductance of the nanowire array capacitors.
- Determination of the interface state profile using the conductance method.
Main Results:
- Demonstrated that a nanowire array capacitor is an effective platform for studying nanoscale interfaces.
- Successfully measured capacitance and conductance of nanowire array capacitors.
- Determined the interface state profile using the conductance method.
Conclusions:
- The developed nanowire array capacitor platform provides a useful and efficient metrology for studying nanoscale metal-oxide-semiconductor physics and device properties.
- This approach enables precise characterization of electronic properties in nanoscale devices.
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