Two-step single slope/SAR ADC with error correction for CMOS image sensor.

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Image Sensor Technology

Background:

• Conventional two-step ADCs for CMOS image sensors demand high resolution in the first stage, leading to increased power and chip size.
• This limitation hinders the development of more efficient and compact image sensors.

Purpose of the Study:

• To present an 11-bit two-step ADC scheme combining single slope and successive approximation register (SAR) architectures.
• To reduce power consumption and chip area in CMOS image sensor ADCs through a novel error correction algorithm.

Main Methods:

• Implemented a two-step ADC with a 3-bit first-stage single slope ADC and a 1-bit redundant bit.
• Utilized a proposed error correction algorithm to combine the redundant bit with an 8-bit SAR ADC output.
• Fabricated the prototype ADC using 0.18 μm CMOS technology.

Main Results:

• The first-stage single slope ADC tolerates up to 3.125% quantization noise, relaxing resolution requirements.
• Achieved a chip area of 7 μm × 500 μm for the prototype ADC.
• Demonstrated an energy efficiency figure-of-merit (FOM) of 125 pJ/sample and chip area efficiency of 84 k μm²·cycles/sample.

Conclusions:

• The proposed two-step single slope/SAR ADC scheme effectively reduces power consumption and chip area in CMOS image sensors.
• The novel error correction algorithm enables relaxed noise performance in the first stage, improving overall efficiency.
• The design offers a promising solution for high-performance, low-power, and compact image sensor applications.