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Updated: May 1, 2026

Production of a Strain-Measuring Device with an Improved 3D Printer
Published on: January 30, 2020
Improved performance of graphene transistors by strain engineering
V Hung Nguyen1, Huy-Viet Nguyen, P Dollfus
1L-Sim, SP2M, UMR-E CEA/UJF-Grenoble 1, INAC, F-38054 Grenoble, France. Center for Computational Physics, Institute of Physics, Vietnam Academy of Science and Technology, PO Box 429 Bo Ho, 10000 Hanoi, Vietnam.
Abstract:
By means of numerical simulation, in this work we study the effects of uniaxial strain on the transport properties of strained graphene heterojunctions and explore the possibility of achieving good performance of graphene transistors using these hetero-channels. It is shown that a finite conduction gap can open in the strain junctions due to strain-induced deformation of the graphene bandstructure. These hetero-channels are then demonstrated to significantly improve the operation of graphene field-effect transistors (FETs). In particular, the ON/OFF current ratio can reach a value of over 10(5). In graphene normal FETs, the transconductance, although reduced compared to the case of unstrained devices, is still high, while good saturation of current can be obtained. This results in a high voltage gain and a high transition frequency of a few hundreds of GHz for a gate length of 80 nm. In graphene tunneling FETs, subthreshold swings lower than 30 mV /dec, strong nonlinear effects such as gate-controllable negative differential conductance, and current rectification are observed.
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