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Facilitating preemptive hardware system design using partial reconfiguration techniques.

Julio Dondo Gazzano1, Fernando Rincon1, Carlos Vaderrama2

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This paper presents a hardware approach for partial reconfiguration in FPGAs, enabling preemptive real-time systems. It supports both explicit and implicit activation for dynamic task scheduling and remote component integration.

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Area of Science:

  • Computer Engineering
  • Embedded Systems
  • Reconfigurable Computing

Background:

  • Partial reconfiguration is key for preemptive systems in FPGA-based control.
  • Real-time systems require task preemption due to critical deadlines and asynchronous events.

Purpose of the Study:

  • To introduce a hardware-based approach for explicit and implicit activation of partial reconfiguration.
  • To enable remote invocation and integration of off-chip components in dynamically reconfigurable SoCs.
  • To present a component location transparency model for system integration.

Main Methods:

  • Developed a hardware-based approach for partial reconfiguration activation.
  • Implemented a reconfiguration service for remote invocation.
  • Designed a model for component location transparency.

Main Results:

  • Successfully demonstrated explicit and implicit activation of partial reconfiguration.
  • Enabled remote integration of off-chip components.
  • Facilitated system integration through location transparency.

Conclusions:

  • The proposed hardware approach effectively manages partial reconfiguration for preemptive systems.
  • The reconfiguration service enhances flexibility and integration capabilities.
  • Component location transparency simplifies the integration of dynamically reconfigurable SoCs.