A 7.5 ps single-shot precision integrated time counter with segmented delay line.

Area of Science:

• Electrical Engineering
• Instrumentation and Measurement
• Semiconductor Devices

Background:

• Accurate time interval measurement is crucial for various scientific and engineering applications.
• Existing time interval counters face limitations in precision and measurement range.
• Advancements in integrated circuit technology enable novel approaches to high-precision timing.

Purpose of the Study:

• To design and test a novel time interval counter with superior single-shot precision.
• To achieve a measurement range of 1 ms with sub-picosecond resolution.
• To integrate the time interval counter into a cost-effective Application Specific Integrated Circuit (ASIC).

Main Methods:

• Combination of direct counting with a two-stage interpolation technique within a single clock period.
• Utilizing tapped delay lines stabilized by a delay-locked loop (DLL) mechanism for both interpolation stages.
• Employing a high-frequency multiphase clock for coarse resolution and a differential delay line for fine resolution.
• Development of a novel segmented delay line with partial overlapping for improved linearity and precision.

Main Results:

• Achieved single-shot precision of 7.5 picoseconds (ps) root mean square (rms).
• Demonstrated a measurement range of 1 millisecond (ms).
• Maximum integral nonlinearity error of fine-stage interpolators was 16 ps (START) and 14 ps (STOP), corrected via statistical calibration.
• The time interval counter was successfully integrated into a single 0.35 μm CMOS ASIC.

Conclusions:

• The proposed time interval counter design effectively achieves high single-shot precision and a wide measurement range.
• The novel segmented delay line and two-stage interpolation are key to overcoming limitations in linearity and resolution.
• Integration into a standard CMOS process offers a cost-effective solution for high-performance timing applications.