Stego on FPGA: an IWT approach.

Area of Science:

• Computer Science
• Electrical Engineering
• Cryptography

Background:

• Image steganography is crucial for secure data transmission.
• Wavelet transforms offer efficient image decomposition for data hiding.
• Hardware acceleration is needed for real-time steganography.

Purpose of the Study:

• To propose a reconfigurable hardware architecture for integer wavelet transform (IWT) based adaptive random image steganography.
• To implement an efficient data embedding scheme using space-filling curves (SFCs).
• To evaluate the performance and resource utilization of the proposed architecture on an FPGA.

Main Methods:

• Utilized Haar-IWT to decompose images into subbands (LL, LH, HL, HH).
• Employed Moore and Hilbert space-filling curves (SFCs) for adaptive data embedding in LH, HL, and HH subbands.
• Selected the SFC yielding the lowest Mean Square Error (MSE) and highest Peak Signal-to-Noise Ratio (PSNR).
• Generated a secret key based on a random walk verdict of image blocks.

Main Results:

• Achieved data embedding in 1.6 µs.
• The system consumed 34% of logic elements, 22% of dedicated logic registers, and 2% of embedded multipliers on a Cyclone II FPGA.
• Demonstrated efficient and secure data hiding with optimized MSE and PSNR.

Conclusions:

• The proposed reconfigurable hardware architecture effectively implements IWT-based adaptive random image steganography.
• The SFC-based embedding strategy optimizes steganographic performance metrics (MSE, PSNR).
• The system offers a practical and efficient solution for secure image data hiding on FPGAs.