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Updated: May 1, 2026

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots
Published on: November 1, 2013
Effect of geometric parameters on the performance of p-type junctionless lateral gate transistors
Farhad Larki1, Arash Dehzangi1, Sawal Hamid Md Ali1
1Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia.
Abstract:
This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension and based on that, the parameters such as threshold voltage, transconductance and resistance in saturation region are analyzed. In addition, simulation results provide a physical explanation for the variation of device characteristics given by the variation of geometric parameters, mainly based on investigation of the electric field components and the carries density variation. It is shown that, the variation of the carrier density is the main factor which affects the characteristics of the device when the device's thickness is varied. However, the electric field is mainly responsible for variation of the characteristics when the source/drain extension is changed.
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