Inverted process for graphene integrated circuits fabrication.

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Graphene field-effect transistors (GFETs) offer promising electronic properties but require scalable fabrication methods.
• Monolithic integration of graphene devices with existing semiconductor technology is crucial for practical applications.

Purpose of the Study:

• To develop a CMOS-compatible, two-layer-routing technology for fabricating GFETs and monolithic graphene integrated circuits (ICs).
• To demonstrate the performance of GFETs and a graphene-based frequency multiplier using the novel fabrication process.

Main Methods:

• Utilized a 200 mm CMOS-compatible two-layer-routing process, inverse to traditional silicon technology.
• Fabricated passive elements in the first metal layer and GFETs with buried gate/source/drain in the second metal layer.
• Employed a gate dielectric with 3.1 nm equivalent oxide thickness (EOT).

Main Results:

• Achieved 500 nm-gate-length GFETs with 80% yield and radio frequency (RF) performance of fT/fmax = 17 GHz/15.2 GHz.
• Demonstrated a high-performance monolithic graphene frequency multiplier functioning up to 8 GHz input and 16 GHz output.
• The frequency multiplier exhibited a 3 dB bandwidth of 4 GHz and a conversion gain of -26 dB.

Conclusions:

• The proposed CMOS-compatible fabrication process enables the successful integration of GFETs and monolithic graphene ICs.
• This technology is suitable for high-frequency applications, as evidenced by the performance of the graphene frequency multiplier.
• The inverse fabrication approach offers a viable pathway for advanced graphene-based electronics.