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Related Experiment Video

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Micro-masonry for 3D Additive Micromanufacturing

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Published on: August 1, 2014

A CMOS ASIC Design for SiPM Arrays.

Samrat Dey¹, Lushon Banks¹, Shaw-Pin Chen¹

¹Electrical Engineering Department, University of Washington, Seattle, WA 98195-2500, USA telephone: (206)685-1600.

IEEE Transactions on Nuclear Science

|May 15, 2014

Summary

Researchers developed a CMOS chip for silicon photomultiplier (SiPM) arrays, improving signal processing with row-column architecture and exploring diagonal summation for enhanced performance and scalability.

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Area of Science:

Instrumentation
Electronics Engineering
Photonics

Background:

Previous work introduced board-level readout electronics for 8x8 silicon photomultiplier (SiPM) arrays.
A row/column summation technique was employed to minimize hardware needs for signal processing.

Purpose of the Study:

To implement a monolithic CMOS chip based on the row-column architecture for SiPM arrays.
To explore diagonal summation and calibration methods for improved accuracy and stability.
To describe a timing pickoff signal for precise pulse alignment within the array.

Main Methods:

Designed a monolithic CMOS chip utilizing a row-column architecture.
Investigated diagonal summation and calibration techniques to mitigate environmental and manufacturing variations.
Developed a timing pickoff signal for spatial channel pulse synchronization.

Main Results:

The ASIC design is scalable for various detector sizes and adaptable to different vendors.
Circuit implementation challenges for interfacing the ASIC with a Phase II MiCES FPGA board and SiPM array were addressed.
Strategies for integrating analog and mixed-signal electronics with SiPMs onto single-chip or multi-chip modules were discussed.

Conclusions:

The developed CMOS chip offers a scalable and flexible solution for SiPM array signal processing.
The integration of advanced signal processing techniques enhances the performance and reliability of SiPM-based systems.
Future integration strategies aim for compact and efficient hybrid or monolithic SiPM-electronics systems.