Modeling and simulation of network-on-chip systems with DEVS and DEUS

Area of Science:

• Computer Engineering
• Electrical Engineering
• Computer Science

Background:

• Traditional VLSI communication architectures like buses and dedicated wires face limitations in performance, scalability, and modularity.
• Networks on-Chip (NoCs) offer superior advantages for Systems on-Chip (SoCs), but their complex design space necessitates robust evaluation methodologies.
• Current NoC evaluation relies heavily on analytical modeling and simulation, lacking a standardized framework.

Purpose of the Study:

• To present an integrated approach for designing and evaluating Networks on-Chip (NoCs).
• To demonstrate the application of the Discrete Event System Specification (DEVS) modeling framework with the DEUS simulation environment for NoC design.
• To address the need for a standardized and modular methodology in NoC evaluation.

Main Methods:

• Integration of the Discrete Event System Specification (DEVS) modeling framework.
• Utilizing the DEUS simulation environment for comprehensive system analysis.
• Leveraging the inherent modularity and sound/complete nature of DEVS and the open-platform capabilities of DEUS.

Main Results:

• The proposed DEVS-DEUS integration provides a standardized and modular framework for NoC design and evaluation.
• This approach facilitates simulation of complex systems at various levels of detail.
• Demonstrates enhanced design productivity and system evaluation capabilities for VLSI SoCs.

Conclusions:

• The DEVS-DEUS integration offers a powerful, standardized solution for designing and evaluating Networks on-Chip.
• This methodology enhances modularity and simulation flexibility, crucial for complex SoC development.
• The approach supports detailed system simulation, improving the overall design and verification process for NoCs.