A distributed Canny edge detector: algorithm and FPGA implementation.

Area of Science:

• Computer Vision
• Image Processing
• Algorithm Optimization

Background:

• The Canny edge detector is a widely used algorithm known for its performance.
• However, its frame-level processing leads to high computational intensity and latency.
• Existing block-level implementations suffer from performance degradation.

Purpose of the Study:

• To develop a block-level Canny edge detection algorithm that maintains performance while reducing latency.
• To address the limitations of frame-level statistics in threshold computation.
• To enable efficient edge detection for high-resolution images and videos.

Main Methods:

• Implemented a distributed Canny edge detection algorithm operating at the block level.
• Developed adaptive threshold computation based on block type and local gradient distribution.
• Utilized a nonuniform gradient magnitude histogram for block-based hysteresis thresholds.
• Synthesized the algorithm on a Xilinx Virtex-5 FPGA with a 32-engine architecture.

Main Results:

• Achieved significantly reduced latency, making it suitable for block-based image codecs and high-resolution content.
• Demonstrated comparable or superior edge detection performance to the frame-level Canny algorithm, particularly in the presence of noise.
• The FPGA implementation processed 512x512 images in 0.721 ms at 100 MHz, outperforming existing FPGA and GPU solutions.

Conclusions:

• The proposed block-level Canny algorithm offers a significant reduction in latency and computational cost.
• It maintains or improves edge detection accuracy, especially under noisy conditions.
• The algorithm is well-suited for real-time, high-resolution image and video processing applications.