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Hardware implementation of 32-bit high-speed direct digital frequency synthesizer
Salah Hasan Ibrahim1, Sawal Hamid Md Ali2, Md Shabiul Islam3
1Department of Electronics, College of Engineering, Diyala University, Baqubah, Diyala 32001, Iraq ; Department of Electrical, Electronics & System Engineering, Faculty of Engineering, Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Malaysia.
Thescientificworldjournal
|July 4, 2014
Summary
This study presents a high-speed direct digital frequency synthesizer using novel techniques to significantly compress the ROM size. The design achieves high frequency resolution, making it ideal for wireless communication systems.
Area of Science:
- Electrical Engineering
- Digital Signal Processing
Background:
- Direct digital frequency synthesizers (DDFS) are crucial for modern wireless communication.
- Existing DDFS designs often face limitations in speed and resource utilization, particularly in ROM size.
Purpose of the Study:
- To design and implement a high-speed DDFS with significantly reduced hardware complexity.
- To enhance the frequency resolution and overall performance of the DDFS.
Main Methods:
- Implemented a modified Brent-Kung parallel adder with pipelining for increased speed.
- Utilized a gated clock technique to minimize registers in the phase accumulator.
- Employed quarter-wave symmetry and angular decomposition for ROM size reduction.
- Leveraged sine-cosine symmetry and XOR gates to further compress the ROM lookup table (LUT).
Main Results:
- Achieved a ROM compression ratio of 534.2:1, reducing the ROM to 368 bits.
- The design incorporates only two adders and two multipliers.
- Attained a high frequency resolution of 0.029 Hz.
Conclusions:
- The proposed techniques enable a highly efficient and compact DDFS design.
- The achieved performance makes this DDFS suitable for demanding wireless communication applications.
- This design offers a compelling solution for high-frequency resolution and reduced hardware footprint.
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