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On the robustness of EC-PC spike detection method for online neural recording
Yin Zhou1, Tong Wu2, Amir Rastegarnia3
1Department of Electrical and Computer Engineering, National University of Singapore, 117583 Singapore, Singapore; Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China.
Background:
Online spike detection is an important step to compress neural data and perform real-time neural information decoding. An unsupervised, automatic, yet robust signal processing is strongly desired, thus it can support a wide range of applications. We have developed a novel spike detection algorithm called "exponential component-polynomial component" (EC-PC) spike detection.
New Method:
We firstly evaluate the robustness of the EC-PC spike detector under different firing rates and SNRs. Secondly, we show that the detection Precision can be quantitatively derived without requiring additional user input parameters. We have realized the algorithm (including training) into a 0.13 μm CMOS chip, where an unsupervised, nonparametric operation has been demonstrated.
Results:
Both simulated data and real data are used to evaluate the method under different firing rates (FRs), SNRs. The results show that the EC-PC spike detector is the most robust in comparison with some popular detectors. Moreover, the EC-PC detector can track changes in the background noise due to the ability to re-estimate the neural data distribution.
Comparison With Existing Methods:
Both real and synthesized data have been used for testing the proposed algorithm in comparison with other methods, including the absolute thresholding detector (AT), median absolute deviation detector (MAD), nonlinear energy operator detector (NEO), and continuous wavelet detector (CWD). Comparative testing results reveals that the EP-PC detection algorithm performs better than the other algorithms regardless of recording conditions.
Conclusion:
The EC-PC spike detector can be considered as an unsupervised and robust online spike detection. It is also suitable for hardware implementation.
