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A high-speed and low-offset dynamic latch comparator.

Labonnah Farzana Rahman1, Mamun Bin Ibne Reaz1, Chia Chieu Yin2

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This study introduces a novel dynamic latch comparator circuit designed for high-speed applications. The new design achieves high speed, low offset voltage, and high resolution while reducing power dissipation.

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Area of Science:

  • Electrical Engineering
  • Integrated Circuit Design

Background:

  • High-speed applications like analog-to-digital converters (ADCs) require efficient comparator circuits.
  • Traditional preamplifier comparator circuits increase power dissipation due to higher current requirements.

Purpose of the Study:

  • To present a novel dynamic latch comparator topology.
  • To enhance speed, resolution, and reduce offset voltage and power dissipation.

Main Methods:

  • Utilized a dynamic latch comparator topology based on latch circuitry.
  • Employed a cross-coupled circuit mechanism with a regenerative latch.
  • Incorporated an input-tracking phase to minimize offset voltage.

Main Results:

  • Achieved an equivalent input-referred offset voltage of 720 μV with a 3.44 mV standard deviation (Monte-Carlo simulations).
  • Demonstrated 8-bit resolution with a power dissipation of 158.5 μW at 1.8 V supply and 50 MHz clock frequency.
  • The comparator has a layout size of 148.80 μm × 59.70 μm.

Conclusions:

  • The proposed dynamic latch comparator offers a high-performance solution for speed-critical applications.
  • The design effectively balances speed, resolution, offset voltage, and power consumption.