Parallel fixed point implementation of a radial basis function network in an FPGA.

Area of Science:

• Artificial Intelligence
• Hardware Implementation
• Digital Signal Processing

Background:

• Radial Basis Function Artificial Neural Networks (RBF ANNs) offer powerful function approximation capabilities.
• Field-Programmable Gate Arrays (FPGAs) provide a flexible platform for hardware acceleration of complex algorithms.
• Online training algorithms enable adaptive and real-time learning for neural networks.

Purpose of the Study:

• To propose and implement a parallel fixed-point RBF ANN on an FPGA.
• To analyze the performance trade-offs (processing time, area) of different fixed-point formats.
• To evaluate the precision of the hardware implementation for nonlinear classification (XOR gate) and function interpolation (sine function).

Main Methods:

• Development of a parallel RBF ANN architecture using fixed-point arithmetic.
• Online training of the RBF ANN utilizing the Least Mean Square (LMS) algorithm.
• Hardware implementation on a Xilinx Virtex-6 FPGA using System Generator, with analysis of resource utilization and timing.

Main Results:

• The fixed-point RBF ANN was successfully implemented and trained online on the target FPGA.
• Analysis of various fixed-point formats revealed trade-offs between precision, processing time, and FPGA resource usage.
• The hardware implementation demonstrated acceptable precision for XOR gate classification and sine function interpolation tasks.

Conclusions:

• The proposed parallel fixed-point RBF ANN on FPGA offers an efficient hardware solution for specific computational tasks.
• Fixed-point implementation presents viable options for balancing performance and resource constraints in hardware ANNs.
• The study validates the feasibility of deploying adaptive RBF ANNs in real-time hardware systems.