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Updated: Apr 22, 2026

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices
Published on: December 7, 2017
Determining the electronic performance limitations in top-down-fabricated Si nanowires with mean widths down to 4 nm
Muhammad M Mirza1, Donald A MacLaren, Antonio Samarelli
1School of Engineering, University of Glasgow , Rankine Building, Oakfield Avenue, Glasgow G12 8LT, United Kingdom.
Abstract:
Silicon nanowires have been patterned with mean widths down to 4 nm using top-down lithography and dry etching. Performance-limiting scattering processes have been measured directly which provide new insight into the electronic conduction mechanisms within the nanowires. Results demonstrate a transition from 3-dimensional (3D) to 2D and then 1D as the nanowire mean widths are reduced from 12 to 4 nm. The importance of high quality surface passivation is demonstrated by a lack of significant donor deactivation, resulting in neutral impurity scattering ultimately limiting the electronic performance. The results indicate the important parameters requiring optimization when fabricating nanowires with atomic dimensions.

