Nanoscale lithography of LaAlO₃/SrTiO₃ wires using silicon stencil masks

We have developed a process to fabricate low-stress, fully crystalline silicon nanostencils, based on ion irradiation and the electrochemical anodization of p-type silicon. These nanostencils can be patterned with arbitrary feature shapes with openings hundreds of micrometers wide connected to long channels of less than 100 nm in width. These nanostencils have been used to deposit (2.5 μm- to 150 nm-wide) lines of LaAlO3 (LAO) on a SrTiO3 (STO) substrate, forming a confined electron layer at the interface arising from oxygen vacancies on the STO surface. Electrical characterization of the transport properties of the resulting LAO/STO nanowires exhibited a large electric field effect through back-gating using the STO as the dielectric, demonstrating electron confinement. Stencil lithography incorporating multiple feature sizes in a single mask shows great potential for future development of oxide electronics.