A 680 nA ECG acquisition IC for leadless pacemaker applications.

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Wearable Health Technology

Background:

• Leadless pacemakers require ultra-low-power integrated circuits (ICs) for long-term implantation.
• Efficient electrocardiogram (ECG) signal acquisition and processing are crucial for pacemaker functionality.
• Minimizing power consumption is a key challenge in developing implantable medical devices.

Purpose of the Study:

• To present a sub-microwatt (sub-μW) ECG acquisition IC tailored for single-chamber leadless pacemaker applications.
• To integrate a low-power, wide dynamic-range ECG readout front-end with an analog QRS-complex extractor.
• To evaluate the performance of the developed IC for low-power heartbeat detection.

Main Methods:

• Designed and implemented a sub-μW ECG acquisition IC with integrated analog QRS-complex extraction.
• Introduced a current-multiplexed channel buffer to drive a self-synchronized SAR ADC.
• Utilized 4 fF/unit capacitors in the SAR ADC design.
• Tested the ASIC's performance using the MIT-BIH arrhythmia database, acquiring nearly 20,000 beats.

Main Results:

• The ASIC achieved an ultra-low power consumption of 680nA.
• Demonstrated high performance metrics: CMRR > 90 dB, PSRR > 80 dB, input-referred noise of 4.9 μVrms (130 Hz bandwidth).
• Achieved rail-to-rail DC offset rejection.
• Attained average Sensitivity (Se) and Positive Predictivity (PP) of >90% for heartbeat detection with input SNR > 6 dB, even with muscle noise.

Conclusions:

• The developed sub-μW ECG acquisition IC is suitable for leadless pacemaker applications.
• The integrated design enables efficient ECG readout and QRS-complex extraction at minimal power.
• The IC demonstrates robust performance for accurate, low-power heartbeat detection in challenging conditions.