An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Real-time electroencephalography (EEG) systems require efficient artifact separation.
• On-line recursive independent component analysis (ORICA) offers a promising approach for artifact removal.
• Existing ORICA implementations face challenges in hardware complexity and efficiency.

Purpose of the Study:

• To propose an efficient 16-channel ORICA processor ASIC for real-time EEG systems.
• To enhance the effectiveness and reduce hardware complexity of ORICA for artifact separation.
• To implement the ORICA processor using TSMC 40 nm CMOS technology.

Main Methods:

• Design of a 16-channel ORICA processor ASIC.
• Integration of an ORICA processing unit and a singular value decomposition (SVD) processing unit.
• Utilization of a deeper pipeline architecture, shared arithmetic processing unit, and shared registers.
• Implementation using TSMC 40 nm CMOS technology.

Main Results:

• The proposed ORICA processor demonstrates enhanced effectiveness and reduced hardware complexity compared to previous work.
• Analysis of 16-channel random signals showed an average correlation coefficient of 0.95452 between original and extracted ORICA signals.
• The ASIC implementation consumes 15.72 mW at a 100 MHz operating frequency.

Conclusions:

• The developed 16-channel ORICA processor ASIC is suitable for real-time EEG systems.
• The design achieves efficient artifact separation with reduced hardware complexity.
• The low power consumption makes it viable for practical portable EEG applications.