NULL convention floating point multiplier

Area of Science:

• Digital Signal Processing
• Computer Arithmetic
• Asynchronous Logic Design

Background:

• Floating point multiplication is essential for high dynamic range and computationally intensive applications demanding precision and low power.
• Existing synchronous multipliers face challenges in meeting stringent power and performance requirements for advanced digital signal processing (DSP).

Purpose of the Study:

• To design and evaluate the first asynchronous NULL convention logic (NCL) based single-precision floating point multiplier.
• To demonstrate the power and performance benefits of NCL for high-precision floating point multiplication in DSP applications.

Main Methods:

• Design of an IEEE 754 single-precision floating point multiplier utilizing the asynchronous NULL convention logic paradigm.
• Implementation and simulation using Xilinx and Cadence tools.
• Comparative analysis of the NCL multiplier against its synchronous counterpart.

Main Results:

• The proposed NCL floating point multiplier achieves a substantial decrease in power consumption compared to synchronous implementations.
• Performance attributes were evaluated through simulations, confirming the viability of the NCL approach for DSP tasks.
• Rounding was intentionally omitted to cater to high-precision requirements.

Conclusions:

• The NCL floating point multiplier represents a novel and power-efficient solution for demanding DSP applications.
• This asynchronous design offers a promising alternative to synchronous multipliers, particularly where low power and high precision are critical.