Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

Area of Science:

• Computer Engineering
• Electrical Engineering
• VLSI Design

Background:

• The increasing density of transistors drives the adoption of System on Chip (SoC) designs.
• Network on Chip (NoC) serves as the essential communication backbone for modern SoCs.

Purpose of the Study:

• To develop a methodology for designing area-optimized, application-specific NoCs.
• To provide hard Quality of Service (QoS) guarantees for real-time traffic flows within NoCs.

Main Methods:

• Derivation of a Mixed Integer Linear Programming (MILP) model.
• Generation of resource-optimal NoC topology and architecture based on traffic and QoS requirements.
• Implementation of micro-architectural features for traffic and latency guarantees.

Main Results:

• Demonstration of area-efficient NoC solutions for industrial and benchmark applications.
• Achieved resource optimization without heuristics, even for complex applications with 48 flows.
• Generation of optimized results within seconds.

Conclusions:

• The proposed MILP-based methodology effectively designs area-optimized NoCs with guaranteed QoS.
• The approach is adaptable to dynamic application traffic variations.
• This technique offers a fast and efficient solution for NoC design challenges in SoCs.