Low Power Systolic Array Based Digital Filter for DSP Applications.

Area of Science:

• Biomedical Engineering
• Digital Signal Processing
• VLSI Design

Background:

• Digital Signal Processing (DSP) is crucial for analyzing biomedical signals like ECG.
• Low power consumption is a key design constraint for portable and implantable biomedical devices.
• Existing filter architectures may not meet stringent power efficiency requirements for continuous monitoring.

Purpose of the Study:

• To investigate the impact of datapath innovations on power consumption in DSP for biomedical applications.
• To propose and evaluate a low-power systolic array-based digital filter for electrocardiogram (ECG) signal processing.
• To reduce leakage power in digital filters used in biomedical signal analysis.

Main Methods:

• Design and implementation of a systolic array-based digital filter using Application-Specific Integrated Circuit (ASIC) methodology.
• Utilizing a TSMC 65 nm technological library node for fabrication.
• Comparative analysis of the proposed filter's power consumption against existing architectures.

Main Results:

• The proposed systolic array filter demonstrates a reduction in leakage power by up to 8.5%.
• Architectural innovations in the datapath contribute to significant power savings.
• Successful implementation using standard ASIC design flow and a 65 nm technology node.

Conclusions:

• The developed systolic array digital filter offers a viable low-power solution for ECG signal processing.
• Datapath architectural innovations are effective in minimizing power consumption for DSP in biomedical contexts.
• This approach paves the way for more energy-efficient biomedical devices and systems.